机读格式显示(MARC)

• 000 00985cam a2200265 a 4500

• 001 0000437721

• 005 20160120085200.0

• 008 090901r20122010cc a b 001 0 eng d

• 020 __ |a 9787030343802 (pbk.) : |c CNY80.00

• 040 __ |a RUC |c RUC |d JLU

• 090 __ |a TP312/ZM

• 093 __ |a TP312 |2 4

• 099 __ |a CAL 022012088840

• 100 1_ |a Zwolinski, Mark.

• 245 10 |a Digital system design with SystemVerilog = |b System Verilog数字系统设计 / |c Mark Zwolinski.

• 246 31 |a 数字系统设计

• 260 __ |a 北京 : |b 科学出版社, |c 2012.

• 300 __ |a xxv, 367 p. : |b ill. ; |c 24 cm.

• 490 0_ |a 国外电子信息精品著作 (影印版)

• 504 __ |a Includes bibliographical references (p. 347-348) and index.

• 534 __ |p Reprint. Originally published: |c Upper Saddle River, N.J. : Addison-Wesley, c2010. |z 9780137045792.

• 650 _0 |a Verilog (Computer hardware description language)

• 650 _0 |a Electronic digital computers |x Design and construction.

• 650 _0 |a Computer simulation.

• 920 __ |a 211180 |z 1